1. Technical Field
This invention generally relates to the field of semiconductor processing and integrated circuit manufacturing. More specifically, the present invention relates to planarizing semiconductor wafer surfaces.
2. Background Art
Today, our society is heavily dependant on hightech electronic devices for everyday activity. Integrated circuits are the components that give life to our electronic devices. Integrated circuits are found in widespread use throughout our country, in appliances, in televisions and personal computers, and even in automobiles. Additionally, modern manufacturing and production facilities are becoming increasingly dependant on the use of machines controlled by integrated circuits for operational and production efficiencies. Indeed, in many ways, our everyday life could not function as it does without integrated circuits. These integrated circuits are manufactured in huge quantities in our country and abroad. Improved integrated circuit manufacturing processes have led to drastic price reductions and performance enhancements for these devices.
The traditional integrated circuit fabrication process is a series of steps by which a geometric pattern or set of geometric patterns is transformed into an operational integrated circuit. An integrated circuit consists of superimposed layers of conducting, insulating, and device-forming materials. By arranging predetermined geometric shapes in each of these layers, an integrated circuit that performs the desired function may be constructed. The overall fabrication process consists of the patterning of a particular sequence of successive layers.
Integrated circuits are chemically and physically integrated into a substrate material, such as a silicon or gallium arsenide wafer, by combining electrically conductive, semi-conductive, and dielectric (insulating) layers or regions. The layers and regions are arranged to form electronic components or devices such as transistors, diodes, and capacitors. Thousands of these devices are formed essentially simultaneously on the surface of a single wafer of semiconductor material during processing.
Throughout the evolution of integrated circuit manufacturing, integrated circuit designers have had two main objectives: (1) to increase integrated circuit performance (mainly by increasing circuit speed) and (2) to increase the functional complexity of the integrated circuits. From the beginning, reducing the physical size of the individual integrated circuit components was a very effective means of achieving both of these goals. Eventually, the reduction in the size of the integrated circuit devices became somewhat limited by secondary factors including the physical logistics and characteristics of the electrical connections joining the various integrated circuit components. In addition, certain aspects of silicon utilization, chip manufacturing costs, and ease of flexibility for integrated circuit design were also adversely affected by electrical interconnect technology restrictions. The approaches taken to overcoming these obstacles have resulted in the present day design practice of vertical stacking or integration of devices and their associated electrical interconnections, commonly known as multilevel-interconnect schemes. By stacking components vertically, one above the other on different layers, connecting the relatively small individual components is less problematic.
For example, in a typical fabrication process, a layer of aluminum or some other metal is deposited on the surface of the wafer substrate. The metal layer is patterned to form interconnect paths along the surface of the wafer substrate. In most processes, an insulating or dielectric layer is then deposited over the first metal layer. Via openings, or holes, are then created in the dielectric layer and a second metal layer is deposited over the dielectric layer. The second metal layer covers the intervening dielectric layer and fills the via openings in the dielectric layer down to the first metal layer. These filled via openings provide electrical connections between the first and second metal layers. The second metal layer is also patterned to form additional circuit devices and paths. The dielectric layer acts as an insulator between the first and second metal layer.
Typically, the dielectric layer is a layer of silicon dioxide formed by a chemical vapor deposition (CVD) process. The silicon dioxide layer normally has a thickness of approximately one micron. The underlying metal layer is also approximately one micron thick. The silicon dioxide layer covers the metal layer and generally conforms to the topology of the underlying layer. This means that the silicon dioxide layer, after deposition, is characterized by a series of relatively uneven, non-planar steps which generally conform in height and width to the features of the underlying metal layer. This phenomena is known as "pattern factor effect." Each structure used in integrated circuit design has a pattern factor number associated with it that characterizes the pattern factor effect. The pattern factor number of a given structure describes how much of the surface area covered by a given structure is made of metal. For example, if a given structure has a pattern factor of 0.5, that means that the surface area of the wafer covered by the structure is approximately 50% metal. One specific example of a metal structure with a pattern factor number of 0.5 or 50% is known as a "maze." In a typical semiconductor design, there will be multiple metal structures with a wide variety of pattern factor numbers. In addition, as the number of layers increases, the overall unevenness of the surface may be exacerbated by stacking multiple metal structures on top of each other in subsequent layers.
Since the overall process of forming integrated circuits on the surface of wafers is heavily dependant on photo processing techniques such as photolithography, it is imperative that the surface of the wafer be as flat, or planar as possible. This is necessary so that the entire wafer surface is the same distance from the lenses used in photolithography. If the surface of the wafer is not extremely planar, different regions of the surface may be "out of focus." This means that the necessary high resolution patterns cannot be accurately printed on the surface of the wafer and the resulting circuit patterns will not be well defined. This, in turn, frequently produces inoperable circuits on the wafer, thereby reducing yield. To alleviate these problems, the surface of the wafer is typically "planarized" or smoothed off at various stages in the manufacturing process. As additional levels are added to multilevel-interconnection schemes and integrated circuit features are scaled down to submicron dimensions, the required degree of planarization increases. Planarization can be performed on either the metal layers, the dielectric layers, or both.
One method used to provide wafer surface planarity in a dielectric layer includes forming an oxide layer using a material such as borophosphosilicate glass (BPSG) on a wafer surface, then heating the wafer to melt the BPSG and thereby planarize the oxide layer. This technique is commonly referred to as "reflow" and was an effective means of planarizing integrated circuit wafers with comparatively large device geometries. However, as improved semiconductor manufacturing technology allowed for smaller integrated circuit device sizes, reflow methods produced unsatisfactory degrees of planarization.
Most recently, chemical mechanical polishing (CMP) processes have been used to planarize the surface of a wafer during the device fabrication process. The typical CMP process involves holding a thin, flat wafer of semiconductor material against a rotating, wetted, polishing pad surface under controlled surface pressure. A polishing slurry, such as a mixture of either a basic or an acidic solution, is used as a chemical etch component in combination with alumina or silica particles. A rotating polishing head or wafer carrier is generally used to hold the wafer under controlled pressure against a rotating polishing platen. The polishing platen is usually covered with a polishing pad, made from a material such as polyurethane. The CMP process employs both chemical and mechanical processes to remove unwanted material from the surface of the wafer. In one aspect, the liquid portion of the slurry chemically depletes, loosens, or modifies the composition of the material on the wafer which is to be removed. Then, the particles or grit within the slurry, in combination with the rotating polishing pad, physically remove the chemically modified material from the wafer.
The effectiveness of the CMP process to achieve a planar surface is dependant, at least in part, upon its ability to remove material from the undesired high spots on the surface of the wafer faster than the low spots, a characteristic which is commonly referred to as CMP "selectivity." CMP selectivity is typically defined as the ratio of the high area removal rate compared to the low area removal rate. For dielectric materials, it is generally preferred to have CMP selectivity as high as possible. A very high selectivity ratio indicates that only unwanted dielectric material is being removed from the surface of the wafer. A high selectivity ratio is desirable because it allows a thinner oxide layer to be deposited over the surface of the wafer. If the selectivity ratio is low, then a relatively thicker layer of oxide must be deposited to prevent the undesired exposing of the underlying metal layer during the CMP planarization process.
While CMP processing can greatly improve the overall planarity of the wafer surface, the amount of polishing that takes place in a given location is also highly dependant on the underlying topology. As mentioned above, the different types of structures underlying the metal or oxide layer will often have different pattern factors and the surface of the upper layer will generally conform to the physical topology of the underlying layer. The slurry compounds used in most CMP processes will generally polish different areas of the upper layer at different rates, based partially on the pattern factor of the underlying structures. The variations in surface planarity alter the amount of pad pressure over the surface of the layer being polished. This variation in pad pressure can contribute to an uneven polishing rate that will create non-planar surfaces. For example, the area of an oxide layer deposited over an isolated metal line will polish faster than the area of the same oxide layer which is deposited over a wide or large area metal pad.
This means that with a typical dielectric layer deposited over a patterned metal layer, in those areas where a narrow interconnect line (on the order of 1 microns) with a relatively low pattern factor runs across a wide field region (on the order of 1-10 mm), the planarized dielectric can become dramatically thinned from the CMP process as compared to those regions where the metal width is considerably wider (e.g. 50-10 microns) and has a relatively higher pattern factor. In addition, a complex metal structure with a number of very thin lines spaced closely together may have a relatively high pattern factor. In some instances, thinning of the dielectric layer can reach a point where the underlying metal layer becomes exposed and circuit failure results. Further, the thickness of the oxide layer will vary significantly based on the type of metal structure underlying the oxide layer and this may also inhibit uniform and effective planarization of the oxide layer.
When planarizing a metal layer, the nature of the problem is slightly different. When the CMP process is applied to the surface of a metal layer deposited over a patterned oxide layer, the areas of the metal layer deposited over oxides structures with a relatively higher pattern factor tend to polish slower than the areas of the metal layer where the underlying oxide structures have a lower pattern factor. This phenomena is know as "dishing." If the dishing is severe enough, then too much of the metal layer may actually be polished away in certain spots, once again resulting in circuit failure. Therefore, even when planarizing a metal layer, CMP rate and selectivity are still critical factors.
One method used for controlling the CMP process to provide more planar wafer surfaces is to place nitride, amorphous carbon, or some other material which is relatively resistant to the CMP process over portions of the oxide layer. This material typically has a relatively high dielectric constant and is known as a "polish stop." When the oxide layer has been planarized to the level of the polish stop, the CMP process is slowed. A polish stop will, theoretically, prevent the removal of the oxide layer beneath the polish stop material. By placing polish stops at appropriate locations on the wafer, a relatively planar surface can be achieved. However, the inclusion of carbon or other polish stop materials in the wafer can have adverse effects on the dielectric capabilities and capacitance of the oxide layer, especially in certain high frequency integrated circuit designs. This makes the use of polish stops unsuitable for many applications. In addition, the polish stop may not actually prevent oxide removal but may only slow the CMP process temporarily. If the surface of the polish stop is exposed to the CMP process long enough, it will eventually break down and wear through.
As the dimensions of the circuits become smaller, and the number of layers used in creating an integrated circuit wafer increase, the problem with consistent, controllable CMP planarization rates has become more critical. Now that submicron dimensions are typical for integrated circuit devices, and six or more layers of deposited materials on integrated circuit wafers are common, prior planarization methods are increasingly inadequate and significantly hinder further advances in integrated circuit manufacturing. In addition, the nature of the oxides used in integrated circuit manufacturing have evolved and changed significantly in the past few years. These changes have also reduced the effectiveness of existing planarization techniques.
Therefore, there exists a need to provide an improved method of CMP planarization for integrated circuit manufacturing to eliminate non-planar surficial height variations due to the underlying topography of the wafer layers. This improved method of CMP planarization should be more controllable than previous methods and should be adaptable to both the metal and dielectric layers of an integrated circuit wafer. Without additional improvements in CMP processing techniques, further advances in designing and manufacturing complex, multi-layer integrated circuits may be difficult to obtain.